Memory circuit structure and semiconductor process for manufacturing the same

ABSTRACT

A memory circuit structure includes a substrate, a plurality of word lines disposed and evenly-spaced on the substrate, wherein the width of said word lines is F, and a select gate adjacent to the word lines, wherein the width of the select gate is (7+4n)F, and n is zero or positive integer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 14/280,688filed May 19, 2014, which is included in its entirety herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a memory circuit structureand a semiconductor process for manufacturing the same, and moreparticularly, to a semiconductor process for manufacturing a NAND flashcircuit structure using spacer self-aligned double patterning (SADP)scheme.

2. Description of the Prior Art

The principle of a photolithographic process is to transfer a circuitpattern on a mask to a wafer by a method of exposure and development,thereby producing specific circuit patterns on the wafer. However, withthe trend towards scaling down the semiconductor products, theconventional photolithographic technologies face formidable challenges.Take mainstream ArF excimer laser method with wavelength of 193 nm, forexample, the reachable minimum half-pitch of a transistor deviceproduced by this kind of light source during exposure in thephotolithographic process is 65 nm. By incorporating the well-knownimmersion lithography technology, the reachable half-pitch maybe furtherreduced to 45 nm, which is almost the physical limitation in thephotolithographic processes. For this reason, if the half-pitch of thesemiconductor device need to go under 45 nm, the industry needs toutilize more advanced photo-lithographic technologies, such as a doublepatterning technology, an extreme ultra violet (EUV) technology, amaskless photolithography (ML2) technology or a nano-imprint technology,etc.

Double patterning is one of most mature methods within theaforementioned various advanced photolithography technologies. Thedouble patterning technology enables the use of current availablephotolithographic tools to produce desired finer circuit patterns,without the requirement of purchasing extremely expensive advancedphotolithography tools, thereby avoiding huge investments. As the doublepatterning technology and relevant equipment gradually mature in theindustry, the 193 nm immersion lithography technology once limited bythe physical limits can be further applied to the advanced process nodesof 32 nm, or even 22 nm, thereby becoming the mainstreamphotolithographic technology for the next semiconductor generation.

The principle of the double patterning technology is to separate onecompact semiconductor circuit pattern into two alternative orcomplementary circuit patterns. The two separate patterns will betransferred respectively by the photolithographic process and then becombined on one wafer to obtain the final completed circuit pattern. Theuse of double patterning technology in nowadays NAND flash processes canproduce word lines or bit lines with intervals smaller than 28 nm,thereby significantly improving the memory capacity in memory blocks.

With regard to the application of conventional self-aligned doublepatterning technology in the manufacture of the NAND flash memory,especially in the manufacture of word lines and select gates in thestring area, since the widths of circuit features and/or the intervalstherebetween are scaled down to dozens of nanometer, the micro-loadingeffect resulting from the different densities of the circuit features inthe processes may be significantly amplified, so that it is difficult toform the pattern features with good profile characteristics, such ascritical dimension uniformity (CDU), line width roughness and line edgeroughness, etc., in both the open areas and the dense areas of thecircuit pattern. To solve this problem, the common solution in theindustry is to dispose additional dummy patterns, ex. dummy word lines,at the boundary between dense regions and open regions, such as theboundary between word line patterns and select gate patterns in a stringarea. The dummy patterns may serve as a sacrificial structure to replacethe non-uniformed circuit features formed by using conventional doublepatterning method, so that the patterns other than the dummy patterns inthe layout may have uniform circuit profiles and characteristics.

In addition to the above-mention approach of dummy patterns, certainprocess schemes are developed in the industry, which features the use ofregular patterns to manufacture circuit pattern with different widths.Please now refer to FIG. 1, which schematically depicting a processscheme for manufacturing a select gate using regular patterns in priorart. As shown in FIG. 1, a poly-silicon layer 102 is formed on asubstrate 10 to form word lines and select gates. A plurality of spacers14 manufactured by double patterning method are formed on thepoly-silicon layer 12 to define the pattern of word lines. A flat layer16 made of planarizable material (ex. an anti-reflective layer) coversthe spacers 14 and poly-silicon layer 12. In this process scheme, aphotoresist 18 is disposed on the flat layer 16 to define desired selectgate region. The photoresist 18 would cover several spacers 14, andpreferably, the edges of photoresist 18 are located respectively on thetwo spacers and do not extend beyond. The select gate and correspondingword lines manufactured by this process scheme would have regularspacing.

However, it is known to those skilled in the art that the photoresist isimpossible to be 100 percent precisely located on the predeterminedposition. To define by the exposure limitation value F of thephotolithographic tool, as it can be obviously known from FIG. 1, thephotoresist 18 is possible to have an F/2 offset. The F/2 offset maybehalf the spacing d between the word lines in current semiconductortechnology level, which the dimension of the word line may be configuredat several dozens of nanometers. In such severe overlay shift, thespacing of finally-made select gate and adjacent word lines would beseverely out of spec and impact the electrical performance of thedevice. Therefore, it is still urgent to those of skilled in the art todevelop or improve the conventional double patterning scheme for therequirement of nano-scale width and density in the semiconductortechnology nowadays.

SUMMARY OF THE INVENTION

As an improved scheme to conventional skills, a novel memory circuitstructure and semiconductor process for manufacturing the same areprovided in the present invention. The process is an improved positiveself-aligned double patterning (P-SADP) scheme in the semiconductortechnology. With specific process flow, uniform line patterns may beformed in the string of the memory circuit layout. It is unnecessary todispose additional dummy patterns in the layout like those used inconventional process schemes. The advantage of the present invention isthat line structures with different widths can be formed by usingregular and uniform patterns and the complexity of process scheme is,therefore, reduced.

One object of the present invention is to provide a semiconductorprocess for manufacturing particular patterns. The process includes thesteps of sequentially forming a target layer and a plurality ofevenly-spaced core bodies having uniform width on a substrate,conformally forming a hard mask layer on the target layer and corebodies so that a plurality of recesses are formed between two adjacentcore bodies in the hard mask layer, forming a first photoresist on thehard mask layer wherein the first photoresist covers a predeterminedregion encompassing at least two core bodies and at least one recess,performing a first etch process using the first photoresist as an etchmask to remove the hard mask layer outside the predetermined region sothat the core bodies outside the predetermined region are exposed,removing the exposed core bodies to expose underlying target layer,forming a second photoresist on the hard mask layer in the predeterminedregion, wherein the second photoresist at least encompasses all ofrecesses in the predetermined region, and performing a second etchprocess using remaining hard mask layer and the second photoresist as anetch mask to pattern the target layer.

Another object of the present invention is to provide a memory circuitstructure including a substrate, a plurality of word lines disposed andevenly-spaced on the substrate, wherein the width of said word lines isF, and a select gate adjacent to the word lines, wherein the width ofthe select gate is (7+4n)F, and n is zero or positive integer.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the embodiments, and are incorporated in and constituteapart of this specification. The drawings illustrate some of theembodiments and, together with the description, serve to explain theirprinciples. In the drawings:

FIG. 1 is a cross-sectional view schematically depicting a processscheme for manufacturing a select gate using regular patterns in priorart; and

FIGS. 2-7 are cross-sectional views schematically depicting a series ofmain steps of the semiconductor circuit process in accordance with onepreferred embodiment of present invention.

It should be noted that all the figures are diagrammatic. Relativedimensions and proportions of parts of the drawings have been shownexaggerated or reduced in size, for the sake of clarity and conveniencein the drawings. The same reference signs are generally used to refer tocorresponding or similar features in modified and different embodiments.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof and is shown by way ofillustration and specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient details toenable those skilled in the art to practice the present invention. Itshould be noted that the present invention may utilize otherembodiments, or structural, logical, and electrical changes maybe madewithout departing from the scope of the present invention. Therefore,the following detailed description is not intended to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims. Furthermore, certain terms are used throughoutfollowing description and appended claims to refer to particularcomponents. As one skilled in the art will comprehend, the manufacturersof the semiconductor device may refer to a component as different names,such as spacer, liner, insulators and dielectrics, etc.

The embodiments will now be explained hereafter with reference to theaccompanying drawings to provide a better understanding of the processof the present invention, wherein FIGS. 2-7 are cross-sectional viewsschematically depicting a semiconductor process in accordance with onepreferred embodiment of present invention. The process of the presentinvention is an improved spacer self-aligned double patterning (SADP)scheme, in which detailed steps and features claimed therein can solvethe problem that conventional SADP process can't manufacture uniformcircuit patterns due to the overly limitation of the photolithographictool and, thereby, improve the performance of the devices.

Please refer to FIG. 2. A substrate 100 is first provided as a base forthe semiconductor devices in the structure of the present invention. Atarget layer 102, such as a conductive layer, and a plurality ofevenly-spaced core bodies 104 are sequentially formed on the substrate100. The target layer 102 is configured to be patterned into thecomponents of all kinds of semiconductor devices or conductive circuitsin following processes. For example, in this embodiment, the targetlayer 102 is used to form conductive circuits, such as word lines, bitlines or select gates in a layout of memory circuit. The substrate 100may include silicon substrate, a silicon-containing substrate, aGaN-on-silicon (or other material of Group III-V), a grapheme-on-siliconsubstrate or a silicon-on-insulator (SOI) substrate and so on, but notlimited to a semiconductor substrate. The concept of the presentinvention may also be applied to other technical fields, such as thefield of display panel. For example, the substrate may be an insulatingglass substrate or a quartz substrate. The material of the target layer102 may include, but is not limited to, a conductive material, such aspolycrystalline silicon, amorphous silicon, salicide or metal material,and it may also be a semiconductor material or an insulating material,such as tetra-ethoxysilane (TEOS). The material of the core bodies 104may include, but is not limited to, silicon nitride, silicon oxide,polycrystalline silicon and amorphous silicon. The core bodies 104 andthe target layer 102 should have different etch selectivity ratio. Thatis, the core bodies 104 and the target layer 102 would have differentetching rates in the same etch process, so that core bodies 104 may beselectively removed in the process.

Refer again to FIG. 2. In the embodiment, a plurality of core bodies 104may be formed by patterning a core layer (not shown) using aphotolithographic process and an etching process. The core bodies 104are in the form of a plurality of evenly-spaced lines when viewed fromthe top, such as the word lines in NAND string of a memory layout. Theabove-mentioned photolithographic process and etching process arewell-known skills in the art, thus redundant description is hereinomitted for simplicity. The width of core body 104 may be set at theexposure limit value F of the photolithographic tool used in theprocess. For example, mostly-used ArF excimer laser stepper (with anexposure wavelength of 193 nm) is currently utilized to manufacture theline feature with critical dimension (CD) of 56 nm, thus the exposurelimit value F in this example is 56 nm. In the embodiment, the spacingbetween the core bodies 104 may be set at the value triple the width Fof the core body 104, i.e. 3F. In such configuration, the target layer102 may be transformed into smaller, evenly-spaced pattern features,such as regularly-arranged word lines and bit line in NAND string, withuniform width in following SADP process. Detailed steps will be providedin the following embodiment.

It may be understood from FIG. 2 that the photoresist patterns used todefine core bodies 104 in the present invention are regular pattern withuniform size and density. For example, the width of all core bodies 104are identically F, and all spacing between each core body 104 isidentically 3F. The above-mentioned uniform photoresist pattern cansignificantly mitigate the micro-loading effect resulted from thepattern features with different densities. Moreover, in otherembodiment, a trimming process may be further performed to reduce thewidth of core bodies 104 to manufacture even finer line structure infollowing processes.

Please now refer to FIG. 3, after core bodies 104 are defined, adeposition process is performed on the substrate 100 to form a spacermaterial layer 106. The spacer material layer 106 is conformally formedon the surface of target layer 102 and each core body 104 by, forexample, atomic layer deposition (ALD), thus uniform thickness may beeasily achieved. In such configuration a recess 107 will be formedbetween each core body 104 after the deposition. In the embodiment, thethickness of the spacer material layer 106 is set at the value the sameas the width F of core body 104. The recess 107 therebetween wouldaccordingly have the same width F (=3F−F−F). This configuration isessential to form the pattern feature with identical width and spacingin following processes. In the embodiment of the present invention, thematerial of the spacer material layer 106 may include, but is notlimited to, silicon nitride, silicon oxide or polycrystalline silicon,etc. The spacer material layer 106 and the core layer 104 should havedifferent etch selectivity ratio. That is, the core bodies 104 and thespacer material layer 106 would have different etching rates in one etchprocess, so that core bodies 104 may be selectively removed according tothe scheme. In the process scheme of the present invention, the spacermaterial layer 106 is configured to form spacers at both sides of eachcore bodies. The thickness of the spacer material layer 106 would bepreferably set at the value the same as the width of finally-formeddesired smaller pattern (ex. word lines).

Refer again to FIG. 3, after the conformal spacer material layer 106 isformed, optionally, a flat layer 108 maybe formed on the spacer materiallayer 106 to provide a flat surface. The flat layer 108 may be a bottomanti-reflective coating (BARC) or a tri-layer structure to provide aplanarized profile. A photoresist 110 (referred hereinafter as firstphotoresist) is then formed on the flat layer 108. In the embodiment,the first photoresist 110 covers a predetermined region R1 which is usedto define the desired larger pattern features, such as a select gate incorresponding layout of memory circuit. Since the first photoresist 110is used to define larger pattern features, the predetermined region R1would substantially encompass at least two core bodies 104 (ex. two corebodies are encompassed in the embodiment). The number of encompassedcore bodies 104 depends on the width of desired larger pattern featuresto be defined. The planarization condition provided by the flat layer108 may help to form the first photoresist 110 on the substrate morereliably, and the anti-reflection effect may help to define thephotoresist patterns more precisely in following photolithographicprocess. On the other hand, the dashed frames shown in FIG. 3 representthe overlay shift of the first photoresist 110 offset respectively toleft and right. To define the overlay shift behavior by theabove-identified exposure limit value F of the photolithographic toolused in the process, the largest offset is set at value of F/2. Thisconfiguration implies that the first photoresist 110 would not coverbeyond the recesses 107 at both sides of the predetermined region R1.Therefore, the pattern definition would not be affected by inevitableoverlay shift. It should be noted that the flat layer 108 is unnecessaryon certain conditions. The first photoresist 110 may be formed directlyon the spacer material layer 106 without the flat layer 108.

Please now refer to FIG. 4. After the flat layer 108 is formed and thepredetermined region R1 is defined by the first photoresist 110, an etchprocess E1 (referred hereinafter as first etch process) is thenperformed using the first photoresist 110 as an etch mask. In theembodiment, the first etch process E1 is an anisotropic etch backprocess, which may remove a portion of the flat layer 108 and the spacermaterial layer 106 with a certain thickness. More specifically, it maycompletely remove the spacer material layer 106 on all core bodies 104outside the predetermined region R1 and expose those core bodies 104.The spacer material layer 106 and the core bodies 104 within thepredetermined region R1 are intact in this etch step because they areprotected by the first photoresist 110. It can be known from FIG. 4 thata portion of flat layer 108 remains in the recesses 107 defined by thespacer material layer 106 after the first etch process E1.Alternatively, there maybe no remaining flat layer in the recesses 107.The spacer material layer 106 is divided into several spacers 106 a inconcave shape because the core bodies 104 are exposed, wherein eachspacer 106 a has a recess 107 formed thereon.

Please now refer to FIG. 5. After the first etch process E1 isperformed, the first photoresist 110, remaining flat layer 108 andexposed core bodies 104 on the substrate are then removed, therebyforming several protruding, concave-shaped spacers 106 a. The recess 112between the spacer 106 a exposes the underlying target layer 102. In theembodiment, since the predetermined region R1 encompasses at least twocore bodies 104, the spacer material layer 106 would have at least onerecess 107 formed thereon. In order to prevent the following etchprocess etch through the recess 107 in the predetermined region(s) R1and impact the definition of the larger pattern, another photoresist 114(referred hereinafter as second photoresist) is formed on the spacermaterial layer 106 in the predetermined region R1 to serve as a mask. Inthe embodiment, the region encompassed by the second photoresist 114maybe smaller than the predetermined region R1. However, in order toprotect the underlying structures, the second photoresist 114 shouldencompass at least all the recesses in the predetermined region R1, asshown in FIG. 5.

Please now refer to FIG. 6. After a number of core bodies 104 areremoved and the second photoresist 114 is formed, an etch process E2(referred hereinafter as second etch process) is further performed usingthe remaining spacer material layer 106 and the second photoresist 114as a mask. In the embodiment, the second etch process E2 is also ananisotropic etch back process, which may remove a portion of the spacermaterial layer 106 and the exposed target layer 102 thereunder with acertain thickness. More specifically, it may completely remove thespacer material layer 106 under the recesses 107 outside thepredetermined region R1, so as to expose and etch the target layer 102under those recesses 107. Please note that the second etch process E2has higher etching rate to target layer 102 than to the spacer materiallayer 106, thus only the relatively thinner portion of the spacermaterial layer 106 under the recesses 107 outside the predeterminedregion R1 would be completely removed, while other relatively thickerportion of the spacer material layer 106 would not be completelyremoved. Moreover, since the region under the recesses 107 in thepredetermined region R1 is protected by the second photoresist 114, notarget layer 102 in said region would be exposed and etched, thus thedesired larger pattern features to be defined in the predeterminedregion R1 may be maintained. In such configuration, the concave-shapedspacer 106 a outside the predetermined region R1 would graduallytransform into smaller, evenly-spaced spacers 106 b (i.e. the desiredsmaller pattern to be defined, such as word lines) with uniform widthduring the second etch process E2. Moreover, in such configuration, nospacer material layer in the predetermined region R1 is etched throughand exposes the underlying target layer, thus desired larger patternfeatures (ex. a select gate pattern) defined in whole predeterminedregion R1 may be maintained.

The second etch process E2 would continue to etch the target layer 102using the pattern formed in the process as a mask, as shown in FIG. 6,so as to form final circuit structure including smaller pattern features102 b (ex. a plurality of word lines) with uniform width F and spacing Fand a larger pattern feature 102 a (ex. a select gate) as shown in FIG.7. The semiconductor process provided by the present invention is,accordingly, completed.

The final pattern formed by the target layer after a series of processsteps provided above would include smaller pattern features with uniformprofile. It is unnecessary like those commonly used in conventionalprocess schemes to dispose one or more dummy patterns (ex. sacrificialword lines) at both sides of the circuit region adjacent to thepredetermined position of the select gates at the start of the patterndefinition, thus available space for circuit layout may be significantlyincreased. The advantage of the present invention fundamentally derivefrom the configuration that all kinds of patterns formed in the seriesof process steps are defined and transformed by evenly-spaced corebodies 104 shown in FIG. 2. The condition of uniform pattern density ofthose core bodies can significant mitigate the micro-loading effect whenmanufacturing nano-scale fine line pattern. Moreover, in the processsteps, the requirement of the first photoresist 110 is to encompass atleast two core bodies 104, thus the overlay shift window may beincreased up to 1.5F, and the requirement of the second photoresist 114is to encompass the recesses 107 in the predetermined region R1, thusits overlay shift window may also be increased up to 1.5F. Both overlayshift windows are larger than the exposure limit F of photolithographictool nowadays, thus common overlay shift issue in prior may be properlysolved.

On the other hand, since the semiconductor process of the presentinvention is based on regular patterns, the defined circuit patternwould have specific sizes and features. For example, as shown in FIG. 5,the predetermined region R1 encompasses two core bodies, which istotally a region of 7F width on the substrate, including the width oftwo core bodies (2F), the thickness of two spacers (2F) and a spacingbetween the core bodies (3F). If the predetermined region R1 encompassesmore core bodies 104, as shown in the figure, an additional region R2with 4F width would be defined for each more core body 104 encompassed.In such configuration, the width of the predetermined region R1 in theembodiment may be represented by (7+4n)F, which is also the width of thefinally-made larger pattern features 102 a. The spacing between thelarger pattern feature 102 a and the smaller pattern features 102 b is(2n+1)F, wherein n is zero or positive integer.

Accordingly, the semiconductor process provided by the present inventionmay manufacture circuit structure with particular patterns. As shown inFIG. 7, the circuit structure may include: a substrate, a plurality ofword lines disposed and evenly-spaced on the substrate with uniformwidth F, and a select gate adjacent to the word lines, wherein the widthof the select gate is (7+4n)F, and the spacing between the select gateand the word lines is (2n+1)F, wherein n is zero or positive integer.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A memory circuit structure, comprising: asubstrate; a plurality of word lines disposed and evenly-spaced on saidsubstrate and, wherein the width of said word lines is F; and a selectgate adjacent to said word lines, wherein the width of said select gateis (7+4n) F, and n is zero or positive integer.
 2. A memory circuitstructure according to claim 1, wherein the spacing between said selectgate and said word lines is (2n+1)F.